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HD74LS192
Synchronous Up / Down Decade Counter (dual clock lines)
REJ03D0454-0200 Rev.2.00 Feb.18.2005 Synchronous operation is provided by having all flip-flops clocked simultaneously so that the output change coincidently with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. The outputs of the four master-slave flip-flops are triggered by a low-to-high-level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is high. This counter is fully programmable; that is, each output may be preset to either level by desired data at the data inputs while the load inputs is low. The output will change to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. A clear input has been provided which forces all outputs to the low level when a high level is applied. The clear function is independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements. This reduces the number of clock drivers, etc., required for long words. This counter was designed to be cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up-and downcounting functions. The borrow output produces a pulse equal in width to the count-down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the count up input when an overflow condition exists. The counters can be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs respectively of .the succeeding counter.
Features
* Ordering Information
Part Name HD74LS192P HD74LS192FPEL Package Type DILP-16 pin SOP-16 pin (JEITA) Package Code (Previous Code) PRDP0016AE-B (DP-16FV) PRSP0016DH-B (FP-16DAV) Package Abbreviation P FP Taping Abbreviation (Quantity) -- EL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Rev.2.00, Feb.18.2005, page 1 of 10
HD74LS192
Pin Arrangement
Data B Input QB Outputs QA Count Down Count Up QC Outputs QD GND 7 8
QD D C
1
B
16
QB QA A Clear
VCC Data A Clear Borrow Carry Load Data C Data D Inputs Outputs Inputs
2 3 4 5 6
15 14 13 12 11 10 9
Inputs
Count Borrow Down Count Up QC Carry Load
(Top view)
Rev.2.00, Feb.18.2005, page 2 of 10
HD74LS192
Block Diagram
Borrow Output Data Input A Down Count Up Count QA T QA Carry Output
Output QA
Data Input B QB T QB Output QB
Data Input C QC T QC Output QC
Data Input D Clear QD T QD Output QD
Load
Absolute Maximum Ratings
Item Supply voltage Input voltage Power dissipation Storage temperature Symbol VCC VIN PT Tstg Ratings 7 7 400 -65 to +150 Unit V V mW C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Rev.2.00, Feb.18.2005, page 3 of 10
HD74LS192
Recommended Operating Conditions
Item Supply voltage Output current Operating temperature Clock frequency Pulse width Setup time (Clear) Setup time Hold time Symbol VCC IOH IOL Topr clock tw tsu (CLR) tsu th Min 4.75 -- -- -20 0 20 40 20 3 Typ 5.00 -- -- 25 -- -- -- -- -- Max 5.25 -400 8 75 25 -- -- -- -- Unit V A mA C MHz ns ns ns ns
Electrical Characteristics
(Ta = -20 to +75 C)
Item Input voltage Symbol VIH VIL VOH Output voltage VOL IIH IIL II Short-circuit output current Supply current** Input clamp voltage IOS ICC VIK min. 2.0 -- 2.7 -- -- -- -- -- -20 -- -- typ.* -- -- -- -- -- -- -- -- -- 19 -- max. -- 0.8 -- 0.4 0.5 20 -0.4 0.1 -100 34 -1.5 Unit V V V V A mA mA mA mA V Condition
VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = -400 A IOL = 4 mA VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V IOL = 8 mA VCC = 5.25 V, VI = 2.7 V VCC = 5.25 V, VI = 0.4 V VCC = 5.25 V, VI = 7 V VCC = 5.25 V VCC = 5.25 V VCC = 4.75 V, IIN = -18 mA
Input current
Notes: * VCC = 5 V, Ta = 25C ** ICC is measured with all outputs open, clear and load inputs grounded, and all other inputs at 4.5 V.
Switching Characteristics
(VCC = 5 V, Ta = 25C)
Item Maximum clock frequency Symbol max tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Inputs Outputs min. 25 -- -- -- -- -- -- -- -- -- typ. 32 17 18 16 15 27 30 24 25 23 max. -- 26 24 24 24 38 47 40 40 35 Unit MHz ns ns ns ns ns Condition
Count-up Count-down Either Count Load Clear
Carry Borrow Q Q Q
Propagation delay time
CL = 15 pF, RL = 2 k
Rev.2.00, Feb.18.2005, page 4 of 10
HD74LS192
Count Sequence
Clear Load A Data Inputs B C D Count Up Count Down QA QB QC QD Carry Borrow Sequence Illustrated 8 0 7 9 0 1 2 1 0 9 8 7 Count Up Count Down
Clear Preset
Rev.2.00, Feb.18.2005, page 5 of 10
HD74LS192
Testing Method
Test Circuit
VCC
Output 4.5V Borrow CL Up Input Down Output Carry A B C D Load Clear QB Output QC Output QD Same as Load Circuit 1. Same as Load Circuit 1. QA Output Same as Load Circuit 1. Output Same as Load Circuit 1. Same as Load Circuit 1. RL Load circuit 1
P.G. Zout = 50
Notes:
1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H).
Testing Table
Item max Up Count Down Count LoadQ ClearQ From input to output CLR GND GND GND GND GND IN Load 4.5V 4.5V 4.5V 4.5V IN IN* Up IN 4.5V IN 4.5V GND GND Inputs Down A 4.5V GND IN GND 4.5V GND IN GND GND IN GND 4.5V B GND GND GND GND IN 4.5V C GND GND GND GND IN 4.5V D GND GND GND GND IN 4.5V
tPLH tPHL
Note: *. For initialized Outputs QA OUT Up Count Down Count LoadQ ClearQ OUT OUT OUT OUT OUT QB OUT OUT OUT OUT OUT OUT QC OUT OUT OUT OUT OUT OUT QD OUT OUT OUT OUT OUT OUT Carry OUT -- OUT -- -- -- Borrow -- OUT -- OUT -- --
Item max
From input to output
tPLH tPHL
Rev.2.00, Feb.18.2005, page 6 of 10
See Waveforms
HD74LS192 Waveforms 1 max, tPLH, tPHL, (Count Up)
tTLH tTHL 3V 1.3V tPHL (Measure at tn + 2) 1.3V tPHL (Measure at tn + 4) QB 1.3V tPHL (Measure at tn + 8) 1.3V tPHL (Measure at tn + 10) QD (Measure before 1 clock of tn + 10) Carry 1.3V 1.3V VOL tPHL 1.3V tPLH (Measure at tn + 10) VOH tPLH (Measure at tn + 2) VOL VOH 1.3V VOL tPLH (Measure at tn + 4) VOH 1.3V VOL tPLH (Measure at tn + 8) VOH 1.3V VOL 1.3V 0V VOH
Count Up
10%
90% 90% 1.3V 1.3V 10% tw (H) tw (L)
tPLH QA (Measure at tn + 1)
Outputs
QC
Notes:
1. Input pulse; tTLH, tTHL 7 ns, PRR = 500 kHz (Data input). PRR = 1 MHz (except data input) Duty cycle = 50% 2. for max tTLH, tTHL 2.5 ns. 3. tn is reference bit time when all outputs are low.
Rev.2.00, Feb.18.2005, page 7 of 10
HD74LS192 Waveforms 2 max, tPLH, tPHL, (Count Down)
tTLH Count Down
90% 90% 10% 10% (Measure at tn + 1) tPHL
tTHL
tw (H)
tw (L) 3V
1.3V
1.3V
1.3V
1.3V
1.3V
0V tPLH (Measure
at tn + 0)
VOH QA
1.3V 1.3V 1.3V
VOL tPHL (Measure at tn + 4) tPLH (Measure
at tn + 2)
VOH VOL
QB Outputs QC
1.3V
1.3V
tPHL (Measure at tn + 6)
tPLH (Measure
at tn + 2)
VOH VOL VOH
1.3V
1.3V
tPHL (Measure at tn + 2) QD
tPLH (Measure
at tn + 0) 1.3V
1.3V
VOL t (Measure before 1 clock of tn + 0) PHL Borrow tPLH (Measure
at tn + 0)
VOH
1.3V 1.3V
VOL
Notes:
1. for max tTLH , tTHL 2.5 ns. 2. tn is reference bit time when all outputs are high.
Rev.2.00, Feb.18.2005, page 8 of 10
HD74LS192 Waveforms 3 tPLH, tPHL, (Load, ClearQ)
tTLH Clear 10% tTHL 3V 90% 90% 1.3V 1.3V 10% tw (CLR) 20ns Data Inputs (A to D) 10% tTHL Load tPHL Q 90% 1.3V 90% 1.3V 10% 10% tTLH tPLH 1.3V 1.3V 0V tPHL VOH 1.3V 1.3V 1.3V VOL tTLH 90% 1.3V tsu tTHL 3V 90% 1.3V th 10% tsu 0V 3V 0V
Note:
Input pulse: tTLH 7 ns, tTHL 7 ns
Rev.2.00, Feb.18.2005, page 9 of 10
HD74LS192
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
E
A1
A
Reference Symbol
Dimension in Millimeters Min Nom 7.62 19.2 6.3 20.32 7.4 5.06 0.51 0.40 0.48 1.30 0.19 0 2.29 2.54 0.25 0.31 15 2.79 1.12 2.54 0.56 Max
e D E
L
1
A A1
e
bp
e1
b c b c
p 3
e Z ( Ni/Pd/Au plating ) L
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
Reference Symbol
*2
c
Dimension in Millimeters Min Nom 10.06 5.50 Max 10.5
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
D E A2
8 bp x M L1
A1 A bp b1 c
0.00
0.10
0.20 2.20
0.34
0.40
0.46
0.15
1
0.20
0.25
A
c
HE
0 7.50 7.80 1.27
8 8.00
A1
y L
e x y
0.12 0.15 0.80 0.50
1
Detail F
Z L L 0.70 1.15
0.90
Rev.2.00, Feb.18.2005, page 10 of 10
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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